Cypress Semiconductor /psoc63 /FLASHC /CM0_CA_CMD

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Interpret as CM0_CA_CMD

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INV)INV

Description

CM0+ cache command

Fields

INV

FLASH cache invalidation. SW writes a ‘1’ to clear the cache. W sets this field to ‘0’ when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The cache’s LRU structure is also reset to its default state.

Links

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